"Bit Twiddling"

I find graphical manipulation fun. I call it "bit twiddling". Much to my satisfaction, rebuilding the Krakus involved lots of it.

I started with scans of the original model sheets. Since I was rescaling from 1:100 to 1:250, I used my bitmap-based graphics editor (I use L-View Pro) to rescale all of the scanned images to 4/10 of their original size.

Then I pasted the rescaled images into a object-based graphical editor (I use Visio). Using Visio's lines, circles, and rectangles I laid out new geometry on top of the bit-map image. Then I applied color to the lines, circles, and rectangles. Here are those steps for the pilot house:

Note that I reversed the position of the door on the left and lowered the windows' position a bit. I also dropped the glue-tabs (see Tabless Construction).

Then I exported the Visio files back to bit-mapped files for final touch-ups (and printing). This was a problem because there is a bug in my version of Visio. Visio's scaling calculation for exporting to BMP-files was wrong. I had to export as GIF-files and then convert to BMP-Files. The way I figured this out (and I wholeheartedly recommend this) was to put in every drawing a 1-inch by 1-cm rectangle. After exporting, I would count the pixels along the edge of that rectangle and make sure that the count was what I expected.

Checking fit is a crucial aspect during this stage. The way I did it was to build complete cross-sectional schematic of the redesign in Visio. For example, here is part of the schematic drawing related to the pilothouse:

I soon figured out that it is really important to take into account the thickness of the card stock (1/3mm) when designing parts to fit togther properly. Note that the decks (like 66) and the "inside forms" (like 67X) are 1mm thick, ie, are designed to be made up of three card-sheet layers laminated together.

I faced an interesting problem during this phase: When a 1/3mm-thickness part is creased and folded at 90 degrees, how do you properly measure/depict the resulting folded configuration in the schematic. Ie, which of the following is the proper result:

I found choice C to be the most accurate.

Here are the schematics:

(The image is shown in reduced scale;
Click on the image to see actual drawing at 4-times resolution.)